(1) Field of the Invention
The present invention relates to construction of a start-stop synchronous data transmitter and a receiver incorporated therein, and to methods of contention detection, and terminal allocation in a network using these components.
(2) Description of the Related Art
With a conventional start-stop synchronous data transmission system, a 1-bit of digital data is logically fixed to either 1 or 0 based on a transmission speed, and the transmission speed and/or transmission media are increased in order to enhance transmission volume. Although increasing the transmission speed enables the system to improve transmission efficiency per medium, it also requires a high-speed transmitter and receiver, which leads to hardware enlargement as well as cost increase.
A conventional receiver used in the system as shown in FIG. 1 comprises a start bit detector 11, a sample cycle counter 12, a sample point decoder 13, and a latch 14.
Upon receiving serial data, the start bit detector 11 detects a falling edge of a start bit thereof, and the sample cycle counter 12 counts a sample cycle for 1-bit, in turn, the sample point decoder 13 outputs a sample clock signal when it counts a given counting value to the latch 14 which samples the serial data with the sample clock signal.
FIG. 2(A) is a timing chart of the signals in the receiver and an enlarged timing chart for a 1-bit interval is shown in FIG. 2(B). Upon detecting the falling edge of the start bit of serial data RXD (hereinafter, referred to as the RXD), the start bit detector 11 outputs a signal STD (hereinafter, referred to as the STD) to the sample cycle counter 12, whereby it starts to count a clock pulse one after another and outputs the counting value to the sample point decoder 13. In turn, the sample point decoder 13 outputs a sample clock signal SCLK (hereinafter, referred to as the SCLK) for the first time to the latch 14 after a lapse of a given time from the output of the STD, and thereafter, continues supplying the SCLK in every bit cycle to the latch 14. As a result, the latch 14 outputs serial data RXDS (hereinafter, referred to as the RXDS) by sampling the RXD when detecting a rising edge of the SCLK.
Included in a conventional transmission method in the system as shown in FIG. 3 is a control terminal 31, terminals 32-34, all of which are connected to a transmission line. The control terminal 31 controls the terminals 32-34 by transmitting a control command. For instance, it transmits each command to the respective terminals through separate communication or it transmits a command to some of the terminals through broadcast communication. As shown in FIG. 4(A), the control terminal 31 assigns terminals 1-6 to power on, turn up the volume, activate a sensor, set a timer, turn on a fan, and turn on an air-conditioner, respectively through the separate communication or as shown in FIG. 4(B), it assigns the terminals 1-3 and 4-6 to power on and turn up the volume, respectively through the broadcast communication.
Such a method is applied to a pattern control which enables a control terminal to transmit short data to other terminals equipped with a buffer memory with a small capacity.
Although the broadcast communication facilitates the ability to transmit a command simultaneously to the terminals belonging to a group address, it transmits each command to the corresponding terminal as well, therefore reducing the advantage thereof. In addition, the control of the terminals under the command is delayed when the transmission line is not available due to contention.